The present invention relates generally to a semiconductor memory. More particularly, the invention is concerned with a semiconductor memory which is capable of operating with a high S/N ratio and which is suited, preferably, for a high density integration.
The invention is also concerned with a semiconductor multiple-level storage memory which can be implemented with a high integration density and enjoy a high S/N ratio.
In recent years, great emphasis has been towards implementation of integrated semiconductor memories with higher and higher density. Among others, the semiconductor memory including memory cells each composed of one transistor and one capacitor (hereinafter referred to as the one-transistor/one-capacitor memory cell) is suited for integration with a high density because of a relatively small number of the elements constituting the memory cell. This type of high-density integrated semiconductor memory is implemented with memory array configurations which can generally be classified as that of a folded data-line arrangement and an open data-line arrangement, as is described in IEEE Proceedings Part I, Vol 130, No. 3, pp. 127-135 (June 1983). In the folded data-line arrangement, paired data lines, i.e. an intrinsic data line onto which a signal is read out from the memory cell and a data line onto which a reference signal is read out are disposed closely adjacent to each other. By virtue of this arrangement, noise transferred from one and the same word line can be canceled out by the paired data lines. Thus, it is possible to read out even very small or minute signals from the memory cells with a high S/N ratio, ensuring a stable operation of the integrated semiconductor memory. On the other hand, in the case of the open data-line arrangement, the data lines in a pair belong to distinct memory arrays, respectively, with a sense amplifier being disposed therebetween. Consequently, difficulty is encountered in canceling out noise generated within the memory array by the paired data lines. Thus, the open data-line arrangement is inferior to the folded data-line arrangement in respect to the S/N ratio. However, with the open data-line arrangement, it is possible to dispose the memory cells at all of the cross-points or intersections between the data lines and the word lines without omission, whereby the semiconductor memory can be integrated with an increased density. By way of example, with a memory cell structure described in 1986 IEEE ISSCC Digest of Technical Papers, pp. 268-269, in which memory cells are implemented in a groove-like fashion at the cross-points between the word lines and the data lines, integration with high density can be realized.
As will be understood from the above description, although the folded data-line arrangement is excellent in respect to the S/N ratio, it is unsatisfactory in respect to high density implementation of the memory cells because the memory cell can be disposed only at one of the intersections between the paired data lines and the word line. An approach tackling this problem is disclosed in JP-A-58-18715. However, with this known technique, it is impossible to realize the semiconductor multiple-level storage memory by using the one-transistor/one-capacitor memory cells.
At present, a multiple-level storage memory has been proposed as a memory of a large storage capacity and a low power consumption. For taking into consideration such multiple-level storage memory as well, it is contemplated with the present invention to provide also a method of realizing a multiple-level storage memory array. In the conventional semiconductor memory, one digit binary data (one bit data) is stored in one memory cell in terms of either one of two potential levels, i.e. a high potential level or a low potential level. In contrast, the semiconductor multiple-level storage memory is designed to store multiple-level voltages in memory cells for thereby making it possible to store data of plural bits. With this arrangement, the memory storage capacity can significantly be increased. More specifically, quantities of electric charges to be stored in memory cells are classified into m (.gtoreq.3) levels, wherein detection is made to which one of m levels the quantity of electric charge stored in a memory cell belongs. In order to discriminatively identify the data of m levels from one another, it is necessary to detect between which of (m-1) boundaries indicating the levels of the stored charges the quantity of charge as read out lies.
In JP-A-55-14588, for example, there is disclosed a detection method, which will be described below. FIG. 9 of the accompanying drawings shows a circuit disclosed in the above publication for performing the discriminative detection or identification of four-level data. Referring to the figure, a memory cell MC is composed of one capacitor and one MOS transistor, wherein the MOS transistor is driven by a word line W to output the data onto a data line d to which there are connected three sense amplifiers SA.sub.i (i=1, 2, 3). Upon occurrence of a read operation, the data line d is precharged to a potential VDD with input/output lines DQ.sub.i being precharged to reference potentials VR.sub.i (VR.sub.1 &lt;VR.sub.2 -VR.sub.3) for comparison in the precharge cycle. The reference potentials VR.sub.1, VR.sub.2 and VR.sub.3 correspond to three charge boundaries for identifying discriminatively the four data. Upon completion of the precharge cycle with a control signal .phi..sub.A assuming a low level "L", the word line W is set to a high level "H" , whereby data is read out from the memory cell MC, resulting in a lowering somewhat of the level on the data line. It is then determined whether the potential on the data line d is lower than the reference potential VR.sub.1 or lies between the reference potentials VR.sub.1 and VR.sub.2 or between VR.sub.2 and VR.sub.3 or higher than the reference potential VR.sub.3 in correspondence to the quantity of charge stored in the memory cell MC. Subsequently, the sense circuits SA.sub.i are disconnected from the data line d and the input/output lines DQ.sub.i by setting control signals .phi..sub.B and .phi..sub.D to level "L" while .phi..sub.C is being set to "H" to thereby allow the sense circuits SA.sub.i to operate. After the individual sense circuits SA.sub.i have been stabilized, the control signal .phi..sub.A is again set to "H", as a result of which the input/output lines DQ.sub.i assume "H" or "L" level in dependence on the states of the sense amplifiers SA.sub.i.
The semiconductor multiple-level storage memory known heretofore suffers from problems mentioned below. The reference voltages VR.sub.i are supplied by precharging externally of the memory array. In conjunction with this, there is employed as the sense circuit a differential amplifier, the reference voltage of which is set at a fixed level. Consequently, influence of noise components contained only in the signal voltage making appearance on the data line can not be eliminated. In U.S. Pat. No. 3,705,391, there is disclosed a scheme according to which the reference voltage mentioned above is derived by converting a digital signal to an analogue signal by using a resistance ladder network. However, in the case of this known arrangement, the reference voltage remains at a fixed level as well, and thus no noise components appearing on the data line can be eliminated.
In order to invalidate the influence of noise making appearance on the data line, it is required to superpose similar noise components on the reference voltage. To this end, a dummy data line has to be disposed in the vicinity of the data line d to thereby generate the reference voltage by using the dummy data line. However, discriminative detection of m levels requires (m-1) reference voltages. Accordingly, provision of the dummy data lines for the m levels, respectively, will increase the area required for disposition of these dummy data lines which, in turn, means that the very object of the semiconductor multiple-level storage memory, that is to increase the memory capacity, can not be attained.
As a memory array in which dummy data lines are employed without being accompanied with any appreciable increase in the area therefor, there is known a semiconductor multiple-level storage memory capable of storing four levels in a memory cell, which is discussed, for example, in IEEE 1988 CUSTOM INTEGRATED CIRCUITS CONFERENCE, Digest of Technical Papers, pp. 4.4.1-4.4.4. According to the teaching disclosed in this publication, one of paired data lines is used as the data line onto which charge is read out from the memory cell while the other one is used as the dummy data line onto which charge is placed from a dummy cell. However, operations for the data line and the dummy data line differ from each other, and it is required to divide the dummy data line upon occurrence of a read operation. Such being the circumstances, difference in the noise components is produced between the signal voltage on the data line and the reference signal volt e on the dummy data line. Such difference in noise cannot be eliminated by the sense amplifier. Thus, limitation is necessarily imposed to the attempt for realizing a high S/N ratio.